PCI Express 2.0 nears completion

By Stephen Shankland on 10 October 2006

Tags: 2.0 | express | pci | pci express | cards

A two-month clock has begun ticking for the release of PCI Express 2.0, an update designed to help the ubiquitous computer communication technology with virtualization, power management and high-end graphics cards.

PCI Express, version 1.0 of which arrived in 2003, lets customers plug devices such as network adapters into computers. PCI Express 2.0 brings a bevy of changes, starting with a speed boost, according to the PCI Special Interest Group (PCI-SIG) that governs the technology.

The PCI-SIG has released a penultimate edition of the basic PCI Express 2.0 specification to its members in version for comments, and the final version is due after a 60-day comment period, the group plans to announce Monday.

PCI Express differs from conventional PCI, its predecessor, in using a smaller number of high-speed serial communication links rather than a larger number of parallel communication lines that send data synchronized in lockstep.

The central feature of the base version of PCI Express 2.0 is a speed boost. It doubles each serial line's data transfer rate from 2.5 gigabits per second to 5 gigabits per second.

But future enhancements also are in the works. One will support high-end graphics cards that slurp 225 or 300 watts of power, said The 451 Group analyst Greg Quick in a report Friday.

A feature called Input-Output Virtualization (IOV) will make it easier for multiple virtual machines, each with its own operating system, to share PCI devices such as network cards.

And the PCI Express Cable specification will let PCI devices be connected not just with plug-in slots but also with standardised copper cables as long as 10 meters with data transfer speeds of 2.5Gbps per line. The technology is suited for tasks such as adding an input-output expansion module housing numerous network cards to a higher-end server.

Finally, a longer-term effort, code-named Geneseo, will let coprocessor cards such as graphics or encryption accelerators be tightly connected to central processors.

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